M32L1632512A
Clock suspension & DQM operation cycle @ CAS Latency = 2, Burst Length = 4
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
6
8
4
5
7
C L O C K
C K E
C S
R A S
C A S
R a
C a
C b
C c
A D D R
A10
A9
R A
W E
D S F
D Q M
D Q
* N o t e 1
Qb0
Qb1
Dc 0
Qa0
Qa1
Qa2
Qa3
D c 2
tS H Z
tS H Z
R ow Ac t i v e
C l oc k
Sus pen s ion
W r i te
D Q M
R ea d
R ead
R ea d D Q M
C l oc k
W r i te
Sus pens ion
:Do n' t C ar e
*Note : 1. DQM needed to prevent bus contention.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 49/54