M32L1632512A
Burst Read Single bit Write Cycle @ Burst Length = 2, BRSW
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
6
8
4
5
7
C L O C K
C K E
* N o t e
1
H I G H
C S
R A S
* N o t e
2
C A S
C Bc
RA a
C Aa R Bb CA b
RA b
C A d
A D D R
A10
A9
R A c
RA a
R Bb
W E
D SF
D Q M
D Ad1
DAd0
QAa0
QAa0
DAb0 D Ab1
D Bc 0
D Bc 0
D Ad0
DAd1
CL = 3
D Ab0 DAb1
Row A c t i ve
(A -B an k )
R ead
(A - Ban k )
Ro w Ac t i v e
( B- B an k )
Ro w Ac t i v e
( A- B an k )
Pre ch arg e
( A- B an k )
W ri t e
(A - Ban k )
W ri t e wi t h
Read w ith
Auto Pr ec harge
( B- Bank )
Auto Pr ec harge
( A- Bank )
: D on' t C ar e
*Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that RAS should not be violated.
t
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command.
The next cycle is also starts the precharge.
3. WPB function is also possible at BRSW mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 48/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
