M32L1632512A
Self Refresh Entry & Exit Cycle
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
6
8
4
5
7
C L O C K
C K E
* N o t e
2
* N o t e
4
tR C m i n
* N o t e
6
S S
t
*N o t e
3
* N o t e
1
tS S
* N o t e
5
C S
R A S
* N o t e
7
* N o t e
7
C A S
A D D R
A10
A9
W E
D S F
D Q M
D Q
H i - Z
H i - Z
Auto R ef res h
Sel f Refr es h En tr y
Se lf R ef res h E xi t
: D o n' t C ar e
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3.The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode minimum RAS is required before exit from self refresh.
t
TO EXIT SELF REFRESH MODE
4.System clock restart and be stable before returning CKE high.
5. CS starts from high.
6.Minimum RC is required after CKE going high to complete self refresh exit.
t
7.2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit
if the system uses burst refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 51/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
