M32L1632512A
Mode Register Set Cycle
Auto Refresh Cycle
1
2
3
8
9
10
6
1
2
3
0
4
5
7
0
6
4
5
C L O C K
C K E
H I G H
H I G H
C S
* N o t e
2
tR C
R A S
* N o t e
1
C A S
* N o t e
3
Key
A D D R
R a
W E
D SF
D Q M
H i - Z
H i - Z
D Q
N ew
C om m an d
M R S
Ne w C om m an d
Auto R ef res h
: D o n' t C ar e
*Both bank precharge should be completed Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS & WE activation and DSF of low at the same clock cycle with address key will set internal mode
register.
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 52/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
