M32L1632512A
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@ Full Page Only)
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
4
5
6
7
8
C L O C K
C K E
H I GH
C S
R A S
C A S
RAa
CA a
CAb
A D D R
A10
A9
*N o t e
1
* N o t e 1
RAa
W E
D SF
D Q M
*N o t e
2
1
1
DQ C L=2
QAa3
QAa4
QAa2
QAa1
DAb4 DAb5
D Ab0 DAb1 DAb2 D Ab3
QAa0
2
2
QAa3 QAa4
DAb2 DAb3
DAb4 D Ab5
C L= 3
QAa0 QAa1 QAa2
D Ab0 DAb1
R ow A c t i v e
( A-B an k )
Read
(A- Ban k )
Read
(A- Ban k )
Prec harg e
( A- Ban k )
Burst Stop
: D on' t C ar e
*Note : 1. At full page mode, burst is warp-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ’s after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at full page mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 46/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
