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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
Auto Refresh & Self Refresh  
Auto Refresh  
An Auto Refresh command is issued by having CS , RAS and CAS held LOW with CKE and WE HIGH at the rising edge of the  
clock(CLK). All banks must be precharged and idle for tRP(min) before the Auto Refresh command is applied. An address counter,  
internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once  
this cycle has started. When the refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh  
command and the next Bank Active command or subsequent Auto Refresh command must be greater than or equal to the  
tRFC(min).To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh  
interval is provided. A maximum of eight Refresh commands can be posted, meaning that the maximum absolute interval between  
any Refresh command and the next Refresh command is 9 x tREFI  
.
C L K  
C L K  
Auto  
Refresh  
C O M M A N D  
PR E  
C M D  
CK E  
= Hi gh  
t R F C  
t R P  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1  
50/62  
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