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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
Power-Down  
Power-Down is synchronously entered when CKE is registered LOW (no accesses can be in progress). CKE is not allowed to go  
LOW while MRS or EMRS command time, or read or write operation is in progress. CKE is allowed to go LOW while any of other  
operations such as Bank Active, Precharge or Auto Precharge, or Auto Refresh is in progress. The DLL should be in a locked state  
when Power-Down is entered. Otherwise DLL should be reset after exiting Power-Down mode for proper read operation.  
If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power-Down occurs when  
there is a Bank Active command in any bank, this mode is referred to as Active Power-Down. Entering Power-Down deactivates  
the input and output buffers, excluding CLK, CLK , ODT and CKE. Also the DLL is disabled upon entering Precharge Power-Down  
or slow exit Active Power-Down, but the DLL is kept enabled during fast exit Active Power-Down. In Power-Down mode, CKE LOW  
and a stable clock signal must be maintained at the inputs of the device, and ODT should be in a valid state but all other input  
signals are “Don’t Care”. CKE LOW must be maintained until tCKE has been satisfied. Power-Down duration is limited by 9 times  
tREFI of the device.  
The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT command). CKE  
HIGH must be maintained until tCKE has been satisfied. A valid, executable command can be applied with Power-Down exit latency,  
t
XP, tXARD, or tXARDS, after CKE goes HIGH.  
CLK  
CLK  
t
IS tIH  
tIH  
t
IS tIH  
tIH  
tIS  
CKE  
VALID  
NOP  
NOP  
VALID  
VALID  
VALID  
Command  
tCKE  
t
CKE  
t
t
XP,  
tXARD,  
XARDS  
t
CKE  
Enter power-down mode  
Exit power-down mode  
: Don’t care  
Read to Power-Down Entry  
Tx+8  
Tx+9  
T0  
Tx+5  
Tx+6  
Tx+7  
T1  
T2  
Tx+2  
Tx+3  
Tx+4  
Tx+1  
Tx  
CLK  
CLK  
CKE should be kept high until the end of burst operation  
Command  
CKE  
READ  
High  
DQS  
DQS  
BL = 4  
AL + CL  
DoutA0  
DoutA2 DoutA3  
DQ  
DoutA1  
Tx+5  
Tx+7  
Tx+8  
Tx+9  
T0  
Tx+4  
Tx+6  
T1  
T2  
Tx+2  
Tx+3  
Tx  
Tx+1  
CLK  
CLK  
Command  
CKE  
READ  
CKE should be kept high until the end of burst operation  
High  
DQS  
DQS  
BL = 8  
AL + CL  
DoutA0  
DoutA2  
DoutA4 DoutA5  
DoutA7  
DoutA6  
DQ  
DoutA3  
DoutA1  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1  
52/62  
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