ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
< RL= 4 (AL= 0; CL= 4); BL=8 >
T4
T0
T1
T2
T5
T6
T7
T8
T3
CLK
CLK
Bank A
Active
Posted CAS
WRITE A
CMD
Precharg A
NOP
> = tRP
NOP
NOP
NOP
NOP
NOP
AL+2 clks + max(tRTP;2)
DQS,DQS
DQs
CL = 4
RL = 4
AL = 0
DoutA0
DoutA4 DoutA5
DoutA7
DoutA1
DoutA3
DoutA6
DoutA2
>= tRAS
Burst Write Followed by Precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 clocks + tWR
.
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be
issued. This delay is known as a write recovery time (tWR) referenced from the completion of the Burst Write to the Precharge
command. No Precharge command should be issued prior to the tWR delay.
< WL= (RL-1) = 3; BL=4>
T4
T0
T1
T2
T5
T6
T7
T8
T3
CLK
CLK
Posted CAS
WRITE A
Precharg A
CMD
NOP
> = tWR
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
DQs
WL = 3
DinA0
DinA1
DinA2 DinA3
< WL= (RL-1) = 4; BL=4 >
T4
T3
T0
T1
T2
T5
T6
T7
T9
CLK
CLK
Posted CAS
WRITE A
Precharg A
CMD
NOP
NOP
> = tWR
NOP
NOP
NOP
NOP
NOP
DQS,DQS
DQs
WL = 4
DinA0
DinA1
DinA2 DinA3
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 46/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
