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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
< RL= 5 (AL= 2; CL= 3); BL= 4; tRCD = 3 clocks; tRTP <= 2 clocks >  
T4  
T0  
T1  
T2  
T5  
T6  
T7  
T8  
T3  
CLK  
CLK  
Bank A  
Active  
Posted CAS  
READ A  
CMD  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Autoprecharge  
>= tRAS(min)  
Autoprecharge begins  
DQS,DQS  
DQs  
tRC Limit  
CL = 3  
AL = 2  
>= tRP  
RL = 5  
DoutA0 DoutA1  
DoutA3  
DoutA2  
>= tRC  
CLK  
CLK  
Bank A  
Active  
Posted CAS  
READ A  
CMD  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Autoprecharge  
>= tRAS(min)  
Autoprecharge begins  
DQS,DQS  
DQs  
tRP Limit  
CL = 3  
AL = 2  
>= tRP  
RL = 5  
DoutA0 DoutA1  
DoutA3  
DoutA2  
>= tRC  
Write with Auto Precharge  
If A10 is HIGH when a Write command is issued, the Write with Auto Precharge function is engaged. The device automatically  
begins precharge operation after the completion of the burst write plus write recovery time (tWR). The Bank Active command  
undergoing Auto Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied.  
(1) The data-in to bank activate delay time (tWR + tRP) has been satisfied.  
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.  
< WR = 2; BL= 4; tRP = 3 clocks >  
T4  
T0  
T1  
T2  
T5  
T6  
T7  
Tm  
T3  
CLK  
CLK  
Bank A  
Active  
Posted CAS  
WRITE  
Autoprecharge  
CMD  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
A
Auto Precharge begins  
>= tRP  
DQS,DQS  
DQs  
tRC Limit  
>= tWR  
WL = RL-1 = 2  
DinA3  
DinA1  
DinA2  
T5  
DinA0  
>= tRC  
T4  
T0  
T3  
T12  
T6  
T7  
T8  
T9  
CLK  
CLK  
Bank A  
Active  
Posted CAS  
WRITE A  
Autoprecharge  
CMD  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Auto Precharge begins  
tWR + tRP  
DQS,DQS  
DQs  
>= tWR  
>= tRP  
WL = RL-1 = 4  
DinA0 DinA1  
DinA3  
DinA2  
>= tRC  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1 49/62  
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