ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Write data mask by DM
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM, Consistent with the implementation
on DDR2 SDRAM. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is
internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.
Data Mask Timing
T4
T1
T2
T5
Tn
T3
DQS
DQS
Din
Din
Din Din
Din
Din
Din
Din Din
DQ
DM
Write mask Iatency = 0
Example: < WL= 3; AL= 0; BL= 4 >
T4
T0
T1
T2
T5
T6
T7
T8
T3
CLK
CLK
tWR
NOP
WL
WRIT
Command
[tDQSS(min.)
DQS,DQS
]
t
DQSS
DQ
DM
Din0
Din2
WL
[tDQSS(max.)
DQS,DQS
]
tDQSS
Din0
Din2
DQ
DM
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 47/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
