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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
Burst Read Followed by Precharge  
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(tRTP, 2) - 2 clocks.  
For the earliest possible Precharge, the Precharge command may be issued on the rising edge which is “Additive latency (AL) +  
BL/2 clocks” after a Read command. A new Bank Active command may be issued to the same bank after the Precharge time (tRP).  
A Precharge command cannot be issued until tRAS is satisfied.  
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the  
last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4, this is the time from  
the actual read (AL after the Read command) to Precharge command. For BL = 8, this is the time from AL + 2 clocks after the Read  
to the Precharge command.  
< RL= 4 (AL= 1; CL= 3) >  
T4  
T0  
T1  
T2  
T5  
T6  
T7  
T8  
T3  
CLK  
CLK  
Bank A  
Active  
Posted CAS  
READ A  
CMD  
Precharge  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
AL + BL/2 clks  
BL = 4  
DQS,DQS  
DQs  
>= tRP  
CL = 3  
AL = 1  
RL = 4  
DoutA0 DoutA1  
DoutA3  
DoutA2  
>= tRAS  
>= tRTP  
CL = 3  
Posted CAS  
READ A  
Precharge A  
CMD  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
AL + BL/2 clks  
DQS,DQS  
DQs  
BL = 8  
CL = 3  
AL = 1  
RL = 4  
DoutA4 DoutA5  
DoutA7  
DoutA0 DoutA1  
DoutA3  
DoutA6  
DoutA2  
>= tRTP  
< RL= 5 (AL= 2; CL= 3); BL= 4 >  
T4  
T0  
T1  
T2  
T5  
T6  
T7  
T8  
T3  
CLK  
CLK  
Bank A  
Active  
Posted CAS  
READ A  
CMD  
Precharge A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
AL + BL/2 clks  
>= tRP  
DQS,DQS  
DQs  
AL = 2  
RL = 5  
CL = 3  
DoutA0 DoutA1  
DoutA3  
DoutA2  
>= tRAS  
CL = 3  
>= tRTP  
< RL= 6 (AL= 2; CL= 4); BL= 4 >  
T4  
T0  
T1  
T2  
T5  
T6  
T7  
T8  
T3  
CLK  
CLK  
Bank A  
Active  
Posted CAS  
READ A  
CMD  
Precharge A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
AL + BL/2 clks  
>= tRP  
DQS,DQS  
DQs  
AL = 2  
CL = 4  
RL = 6  
DoutA0 DoutA1  
DoutA3  
DoutA2  
>= tRAS  
CL = 4  
>= tRTP  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1 45/62  
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