ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Burst Write followed by Burst Read
< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >
T4
T0
T1
T2
T5
T6
T7
T9
T8
T3
CLK
CLK
Write to Read = CL -1+BL/2+tWTR
NOP
Posted CAS
READ A
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQS
DQS,DQS
AL = 2
WL = RL -1 = 4
CL = 3
RL = 5
> = tWTR
DoutA0
DQ
DinA0 DinA1 DinA2 DinA3
Note: The minimum number of clock from the Burst Write command to the Burst Read command is [CL - 1 + BL/2
+ tWTR]. This tWTR is not a write recovery time (WR) but the time required to transfer the 4 bit write data from
the input buffer into sense amplifiers in the array.
Seamless Burst Write
< RL= 5; WL= 4; BL= 4 >
T4
T0
T1
T2
T5
T6
T7
T8
T3
CLK
CLK
Posted CAS
WRITE A
Posted CAS
WRITE B
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS,DQS
WL = RL-1 = 4
DQs
DinA0 DinA1 DinA2
DinA3 DinB0
DinB3
DinB1 DinB2
Note: The seamless burst write operation is supported by enabling a Write command at every other clock for BL =
4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 42/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
