ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE LOW while holding RAS HIGH at the rising edge of the
clock (CLK). The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus
one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is
registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven low (preamble) one
clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following
the preamble. The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge during write
cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or
8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after
the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time
(tWR).
Write (Data Input) Timing
tDQSL
t
DQSH
DQS
DQS
DQS
DQS
t
WPST
tWPRE
Din3
Din2
DQ
DM
Din1
Din0
t
DH
tDH
t
DS
tDS
Burst Write
< RL= 5 (AL= 2; CL= 3); WL= 4; BL= 4 >
T4
T0
T1
T2
T5
T6
T7
Tn
T3
CLK
CLK
Posted CAS
WRITE A
CMD
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Case1 : with tDQSS(max)
DQS,DQS
t
DQSS
WL = RL -1 = 4
t
DSS
>= tWR
>= tWR
DQs
DinA0 DinA1 DinA2 DinA3
DSH
t
t
DQSS
Case2 : with tDQSS(min)
DQS,DQS
WL = RL -1 = 4
DQs
DinA0 DinA1 DinA2 DinA3
< RL= 3 (AL= 0; CL= 3); WL= 2; BL= 4 >
T4
T0
T1
T2
T5
T6
T7
Tn
T3
CLK
CLK
Bank A
Active
Precharge
CMD
NOP
NOP
NOP
WRITE A
NOP
NOP
NOP
t
DQSS
DQS,DQS
WL = RL -1 = 2
>= tRP
t
WR
DQs
DinA0 DinA1 DinA2 DinA3
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 41/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
