ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Essential Functionality for DDR2 SDRAM
Burst Read Operation
The Burst Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of
the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to
when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The DQS is driven LOW 1
clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of DQS.
Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the MRS and the AL is defined by the
EMRS(1).
Read (Data Output) Timing
tCH
tCL
CLK
CLK
DQS
DQS
t
RPST
t
RPRE
Dout0
Dout1
DQSQ(max.)
Dout2
DQ
Dout3
t
DQSQ(max.)
t
tQH
tQH
Burst Read
< RL= 5 (AL= 2; CL= 3); BL= 4 >
T4
T0
T1
T2
T5
T6
T7
T8
T3
CLK
CLK
Posted CAS
READ A
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
=< tDQSCK
DQS,DQS
AL = 2
CL = 3
RL = 5
DQs
DoutA0 DoutA1
DoutA3
DoutA2
< RL= 3 (AL= 0; CL= 3); BL= 8 >
T4
T0
T1
T2
T5
T6
T7
T8
T3
CLK
CLK
CMD
NOP
NOP
NOP
NOP
READ A
NOP
NOP
NOP
NOP
=< tDQSCK
DQS,DQS
CL = 3
RL = 3
DQs
DoutA4 DoutA5
DoutA3
DoutA7
DoutA6
DoutA0 DoutA1
DoutA2
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 39/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
