ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
Precharge
The Precharge command is used to precharge or close a bank that has activated. The command is issued when CS , RAS and
WE are LOW and CAS is HIGH at the rising edge of the clock. The Precharge command can be used to precharge each bank
respectively or all banks simultaneously. The bank select addresses (BA0, BA1) and A10 are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the Precharge command can be issued.
After tRP from the precharge, a Bank Active command to the same bank can be initiated.
Bank Selection for Precharge by Address bits
A10/AP
BA1
0
BA0
0
Precharge
Bank A Only
Bank B Only
Bank C Only
Bank D Only
All Banks
0
0
0
0
1
1
0
0
1
1
1
X
X
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode, DDR2 SDRAM would ignore all the control inputs.
The DDR2 SDRAM are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP, the device should finish the current operation when this command is issued.
Bank Active
The Bank Active command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock
(CLK). The DDR2 SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank Active
command to the first Read or Write command must meet or exceed the minimum of RAS to CAS delay time (tRCD(min.)). Once
a bank has been activated, it must be precharged before another Bank Active command can be applied to the same bank. The
minimum time interval between interleaved Bank Active command (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (tRRD min).
Bank Active Command Cycle
Tn
T0
T1
T2
Tn+1
Tn+2
Tn+3
ACT
T3
CLK
CLK
Posted
READ
Posted
READ
Command
Address
PRE
PRE
ACT
ACT
Bank A
Row Addr.
Bank B
Row Addr.
Bank A
Col. Addr.
Bank B
Col. Addr.
Bank A
Row Addr.
Bank B
Bank A
t
CCD
Bank A Read begins
Additive latency (AL)
tRCD=1
t
RRD
t
RP
t
RAS
t
RC
Bank B
Precharge
Bank A
Active
Bank A
Precharge
Bank B
Active
Bank A
Active
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 37/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
