ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
6.
t
JIT (cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT (cc) = Max. of | tCK i +1 - tCK i|
tJIT (cc) defines the cycle to cycle jitter when the DLL is already locked.
t
t
JIT (cc, lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
JIT (cc) and tJIT (cc, lck) are not subject to production testing.
7.
t
ERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg).
tERR (nper) is not subject to production testing.
8. These parameters are specified per their average values, however it is understood that the following relationship between
the average timing and the absolute instantaneous timing holds at all times. (Min. and max. of SPEC values are to be used
for calculations in the table below.)
Parameter
Symbol
Min.
Max.
Unit
Absolute clock period
tCK (abs)
tCH (abs)
tCK (avg)(min.) + tJIT (per)(min.)
CH (avg)(min.) x tCK (avg)(min.) +
tCK (avg)(max.) + tJIT (per)(max.)
tCH (avg)(max.) x tCK (avg)(max.)
+ tJIT (duty)(max.)
ps
ps
Absolute clock high pulse width
t
t
t
JIT (duty)(min.)
CL (avg)(min.) x tCK (avg)(min.) +
JIT (duty)(min.)
Absolute clock low pulse width
tCL (avg)(max.) x tCK (avg)(max.)
+ tJIT (duty)(max.)
tCL (abs)
ps
t
Example: For DDR2-1066, tCH (abs)(min.) = (0.48 x 1875ps) - 75 ps = 825 ps
Input Slew Rate De-rating
For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS
(base) and tIH (base), tDH (base) value to the ΔtIS, ΔtDS and ΔtIH, ΔtDH de-rating value respectively.
Example: tDS (total setup time) = tDS (base) + ΔtDS
.
Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF (DC) and the first
crossing of VIH (AC)(min.). Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VREF (DC) and the first crossing of VIL (AC)(max.). If the actual signal is always earlier than the nominal slew rate line between
shaded ‘VREF (DC) to AC region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for de-rating value (see the figure of Slew Rate Definition
Tangent).
Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC)(max.) and the
first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH (DC)(min.) and the first crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line between
shaded ‘DC level to VREF (DC) region’, use nominal slew rate for de-rating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’, the slew rate of a
tangent line to the actual signal from the DC level to VREF (DC) level is used for de-rating value (see the figure of Slew Rate
Definition Tangent).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH / VIL (AC) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH / VIL (AC).
For slew rates in between the values listed in the tables below, the de-rating values may be obtained by linear interpolation. These
values are typically not subject to production test. They are verified by design and characterization.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 20/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
