ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
AC Timing Parameter & Specifications - Contiuned
-2.5
-3
Unit
Note
Parameter
Symbol
Min.
Max.
Min.
Max.
Minimum time clocks remains
ON after CKE asynchronously
drops low
tDELAY
tIS + tCK (avg)+tIH
-
t
IS + tCK (avg)+tIH
-
ns
Output impedance test driver
delay
tOIT
0
12
0
0
12
ns
ns
MRS command to ODT update
delay
tMOD
0
2
12
2
12
2
ODT turn-on delay
ODT turn-on
tAOND
tAON
2
tCK
ps
t
AC(max.) +
700
t
AC(min.)
tAC(max.) + 700
2 x tCK
tAC(min.)
14,16
2 x tCK
ODT turn-on (Power-Down
mode)
tAONPD
t
t
AC(min.) + 2000 +tAC(max.) +
1000
t
t
AC(min.) + 2000 +tAC(max.) +
1000
ps
15,17
,18
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
tCK
ps
t
AC(max.) +
600
t
AC(min.)
tAC(max.) + 600
2.5 x tCK
tAC(min.)
2.5 x tCK
ODT turn-off (Power-Down
mode)
tAOFPD
AC(min.) + 2000 +tAC(max.) +
1000
AC(min.) + 2000 +tAC(max.) +
1000
ps
ODT to Power-Down entry
latency
tANPD
tAXPD
3
8
-
-
3
8
-
-
tCK
tCK
ODT Power-Down exit latency
Note:
1. tDAL[nCLK] = WR[nCLK] + tnRP[nCLK] =WR+RU{tRP[ps]/tCK(avg)[ps]}, where WR is the value programmed in the mode
register set and RU status for round up.
2. AL: Additive Latency.
3. MRS A12 bit defines which Active Power-Down Exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH (AC) level for a rising
signal and VIL (AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL (DC) level for a rising
signal and VIH (DC) for a falling signal applied to the device under test.
6. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input
specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH
calculation is determined by the following equation;
tHP = Min ( tCH (abs), tCL (abs) ), where:
t
CH (abs) is the minimum of the actual instantaneous clock HIGH time;
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 16/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
