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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
Clock Jitter [ DDR2- 1066, 800, 667 ]  
-1.8  
-2.5  
-3  
Parameter  
Symbol  
Unit  
Note  
Min.  
1875  
-90  
Max.  
7500  
90  
Min.  
2500  
-100  
Max.  
8000  
100  
Min.  
3000  
-125  
Max.  
8000  
125  
Average clock period  
tCK (avg)  
tJIT (per)  
ps  
ps  
1
5
Clock period jitter  
Clock period jitter during  
DLL locking period  
t
JIT (per,lck)  
tJIT (cc)  
JIT (cc, lck)  
-80  
80  
-80  
80  
-100  
-250  
-200  
100  
250  
200  
ps  
ps  
ps  
5
6
6
Cycle to cycle period jitter  
Cycle to cycle clock period jitter  
During DLL locking period  
-180  
-160  
180  
160  
-200  
-160  
200  
160  
t
Cumulative error across 2 cycles tERR (2per)  
Cumulative error across 3 cycles tERR (3per)  
Cumulative error across 4 cycles tERR (4per)  
Cumulative error across 5 cycles tERR (5per)  
Cumulative error across  
-132  
-157  
-175  
-188  
132  
157  
175  
188  
-150  
-175  
-200  
-200  
150  
175  
200  
200  
-175  
-225  
-250  
-250  
175  
225  
250  
250  
ps  
ps  
ps  
ps  
7
7
7
7
t
ERR (6-10per)  
-250  
-425  
250  
425  
-300  
-450  
300  
450  
-350  
-450  
350  
450  
ps  
ps  
7
7
n=6,7,8,9,10 cycles  
Cumulative error across  
n=11,12,….49,50 cycles  
Average high pulse width  
Average low pulse width  
Duty cycle jitter  
t
ERR (11-50per)  
tCH (avg)  
tCL (avg)  
tJIT (duty)  
0.48  
0.48  
-75  
0.52  
0.52  
75  
0.48  
0.48  
-100  
0.52  
0.52  
100  
0.48  
0.48  
-125  
0.52  
0.52  
125  
t
t
CK (avg)  
CK (avg)  
ps  
2
3
4
Note:  
1.  
tCK (avg) is calculated as the average clock period across any consecutive 200 cycle window.  
2. tCH (avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.  
3. tCL (avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.  
4. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH  
(avg). tCL jitter is the largest deviation of any single tCL from tCL (avg).  
tJIT (duty) is not subject to production test.  
t
t
t
JIT (duty) = Min./Max. of { tJIT (CH), tJIT (CL)}, where:  
JIT (CH) = { tCH j - tCH (avg) where j =1 to 200}  
JIT (CL) = {tCL j - tCL (avg) where j =1 to 200}  
5.  
t
t
t
t
t
JIT (per) is defined as the largest deviation of any single tCK from tCK (avg).  
JIT (per) = Min./Max. of { tCK j - tCK (avg) where j =1 to 200}  
JIT (per) defines the single period jitter when the DLL is already locked.  
JIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only.  
JIT (per) and tJIT (per, lck) are not subject to production testing.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1 19/62  
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