ESMT
M12S64164A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
11
12
13
14
18
15
16
17
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
C B c
C D b
R A a
R D b
R B c
C A a
B A 0
B A 1
A10/AP
R A a
R B b
R A c
Ddb 1
D db1
* N o t e 1
t
C D L
C L = 2
D Q
QB c0
D D b 0
D D b 0
D D b 2
QAa 3
D D d 3
Q Bc1 QB c2
QAa0 QAa1 QAa2
C L = 3
QAa3
QAa0
D D b 2 D D d 3
QAa1 QAa 2
QB c0
QB c1
W E
D Q M
R e a d
( B - B a n k )
W r i t e
( D - B a nk )
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1. tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 34/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
