ESMT
M12S64164A
Page Read Cycle at Different Bank @ Burst Length = 4
0
1
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C L O C K
C K E
H I G H
* N o t e 1
C S
R A S
* N o t e 2
C A S
A D D R
B A 0
C B b
R A a
R C c
C C c
C A a
C D d
R B b
R D d
B A 1
A1 0/AP
C L = 2
RCc
RAa
RBb
RDd
QAa0
QDd2
QDd0 QDd1
QAa1 QAa2
QBb0 QBb1 QBb2
QCc0 QCc1 QCc2
D Q
C L = 3
QCc2
QDd0 QDd1
QCc1
QBb1 QBb2 QCc0
QAa1 QAa2
QAa0
QBb0
QDd2
W E
D Q M
P r e c h a r g e
( D - B a n k )
R e a d
( B - B a n k )
R e a d
( A - B a n k )
R e a d
( C - B a n k )
R e a d
( D - B a n k )
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( D - B a n k )
P r e c h a r g e
( C - B a n k )
R o w A c t i v e
( B - B a n k )
R o w A c t i v e
( C - B a n k )
P r e c h a r g e
( A - B a n k )
P r e c h a r g e
( B - B a n k )
: D o n ' t C a r e
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 32/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
