ESMT
M12S64164A
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
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19
C L O C K
C K E
C S
R A S
C A S
A D D R
C a
R a
C c
C b
B A 0
BA 1
A 10/AP
D Q
R a
Q a 0
Q a 2
Q a1
Q a 3
Q b 0 Q b1
D c 0
D c 2
t
S H Z
t
S H Z
W E
* N o t e 1
D Q M
Cl ock
S u pe ns i on
W r i t e
D Q M
R o w A c t i ve
Rea d
Re ad
W r i t e
D Q M
R e ad D Q M
W r i t e
Cl o ck
S usp ension
: D o n ' t C a r e
*Note: 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 36/45