ESMT
M12S64164A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
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3
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9
10
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C L O C K
H I G H
C K E
C S
t
R C D
R A S
C A S
* N o t e 2
A D D R
R a
C a
C d
C b
C c
B A0
B A 1
A10/AP
R a
t
R D L
Qa 0
D c 1
D c 1
Q b 0 Q b 1
D c 0
D c 0
C L = 2
Q a 1
Q b 2
Q b 1
D d 1
D d 0
D d 0
D Q
Q a 0
Q b 0
Q a 1
C L = 3
D d 1
t
C D L
W E
* N o t e 1
* N o t e 3
D Q M
Read
( A - Bank )
Read
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
P r e c h a r g e
( A B a n k )
-
: D o n ' t C a r e
Note:
1. To Write data before burst read ends. DQM should be asserted three cycles prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, tRDL before row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 31/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
