ESMT
M12S64164A
Read & Write cycle with Auto Precharge @ Burst Length = 4
0
1
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C L O C K
C K E
C S
H I G H
R A S
C A S
A D D R
R b
C a
C b
R a
B A 0
BA 1
A10/AP
R b
R a
C L = 2
D Q
QAa 2 QAa3
D D b 0 Dd b1
D D b 2 D D d 3
QAa 0 QAa1
QAa0
C L = 3
D D b 0
QAa1 QAa2 QAa 3
Ddb 1
D D d 3
D D b 2
W E
D Q M
Read with
Auto Precharge
( A - Bank )
Write with
Auto Precharge
(D-Bank)
Row Active
A - Bank )
Auto Precharge
Start Point
(D-Bank)
(
Row Active
( D - Bank )
Auto Precharge
Start Point
: D o n ' t C a r e
*Note: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 35/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
