ESMT
M12S64164A
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
0
1
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9
10
11
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19
C L O C K
H I G H
C K E
C S
R A S
C A S
A D D R
C A b
C A a
R A a
B A 0
BA 1
A1 0/AP
R A a
1
1
C L = 2
D Q
QAa 0
QAa1 QAa2
QAb 1 QAb5
QAb2 QAb3 QAb 4
QAa3 QAa 4
QAb 0
2
2
C L = 3
QAa 2
QAa4
QAb5
QAa1
QAa 3
QAb0 QAb1
QAb4
QAb2 QAb 3
QAa0
* N o t e 1
W E
D Q M
R e a d
( A - B a n k )
B u rs t S t o p
R e a d
( A - B a n k )
P r e c h a r g e
( A - B a n k )
R o w A c t i v e
( A - B a n k )
: D o n ' t C a r e
*Note: 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 37/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
