ESMT
M12S64164A
Read & Write Cycle at Same Bank @ Burst Length = 4
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
H I G H
C K E
* N o t e 1
t
R C
C S
t
R C D
R A S
C A S
* N o t e 2
A D D R
C b 0
C a 0
R b
R a
B A 0
B A1
A1 0/AP
C L = 2
R a
R b
Q a 0 Q a 1
Q b 0 Q b 1 Q b 2 Q b 3
Q b 0 Q b 1 Q b 2 Q b 3
Q a 2 Q a 3
* N o t e 3
D Q
t
R D L
C L = 3
Q a 0 Qa 1
Q a 3
Q a 2
* N o t e 3
t
R D L
W E
D Q M
Precharge
( A - Bank )
Read
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Row Active
( A - Bank )
P r e c h a r g e
( A B a n k )
-
: D o n ' t C a r e
*Note: 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2 30/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
