ESMT
(Preliminary)
M12L128324A (2E)
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
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C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
CA b
CA a
RA a
BA1
BA0
RA a
A10/AP
tR D L
* N o t e 1
tB D L
DAa4
DAa2 DAa3
DAa0
DAa1
DAb3 DAb4 DAb5
DAb0 DAb1 DAb2
D Q
W E
D Q M
W ri t e
(A - Ban k )
Burst Stop
W r i t e
( A - Ban k )
Row A c t i ve
( A- B an k )
Precharge
( A- B an k )
:D on' t C ar e
*Note: 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 38/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
