ESMT
(Preliminary)
M12L128324A (2E)
Read & Write cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
R b
C a
C b
R a
BA0
BA1
R a
R b
A10/AP
QAa2
CL = 2
D Q
QAa0 QAa1
QAa3
QAa2
DD d3
DD d3
DD b0 Ddb1
DD b2
DD b2
CL = 3
QAa0 QAa1
DD b0
QAa3
Ddb1
W E
D Q M
W r i t e wi t h
Auto Pr echar ge
( D- B an k )
Auto Pr echar ge
Star t Poin t
(D - Ban k )
Read with
Auto Precharge
( A - Bank )
Auto Pr echar ge
Star t Poin t
Row Active
( A - Bank )
Row Active
( D - Bank )
: D o n ' t C a r e
*Note: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 35/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
