ESMT
(Preliminary)
M12L128324A (2E)
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
16
17
18
0
1
2
5
9
10
11
12
13
14
15
19
3
4
6
7
8
C L O C K
C K E
C S
R A S
C A S
A D D R
R a
C a
C c
C b
BA1
BA0
R a
A10 /AP
* N o t e 2
tR C D
D Q
Qb0 Qb1
tS H Z
Qa0
Qa1
Qa3
tS H Z
Dc 2
Qa2
Dc 0
W E
* N o t e 1
D Q M
W r i t e
D Q M
Cl oc k
Su pen sion
Read
W r i t e
D Q M
Ro w A c t i ve
Read
Rea d D Q M
W r i t e
Cl oc k
Suspension
:D on ' t C ar e
*Note: 1. DQM is needed to prevent bus contention.
2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 36/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
