ESMT
(Preliminary)
M12L128324A (2E)
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
15
16
17
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
RA a
C B c
C D b R B c
CA a
R D b
BA1
BA0
A10/AP
CL = 2
R A c
RA a
RB b
QAa1
QAa0
* N o t e 2
* N o t e 1
tC D L
DD d3
tR C D
DD b0
DD b2
QBc0
QBc2
QBc1
QAa3
Ddb1
QAa0
QAa2
D Q
CL = 3
QBc0 QBc1
QAa1 QAa2
QAa3
DD d3
DD b0 Ddb1 DD b2
W E
D Q M
Read
( B - Ban k )
W r i t e
( D - B an k )
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1. tCDL should be met to complete write.
2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 34/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
