ESMT
(Preliminary)
M12L128324A (2E)
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
1 0
C L O C K
C K E
C S
H I G H
H I G H
* N o t e 2
t
R F C
R A S
* N o t e 1
C A S
* N o t e 3
A D D R
R a
K e y
H I - Z
H I - Z
D Q
W E
D Q M
N e w
C o m m a n d
M R S
N e w C o m m a n d
: D o n ' t C a r e
Au t o Ref re sh
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 41/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
