ESMT
(Preliminary)
M12L128324A (2E)
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C L O C K
C K E
* N o t e 4
* N o t e 2
t
R F C mi n
* N o t e 1
* N o t e 6
* N o t e 3
t
S S
* N o t e 5
C S
R A S
* N o t e 7
C A S
A D D R
B A 0 , B A 1
A10/ AP
D Q
Hi - Z
Hi -Z
W E
D Q M
S e l f R e f r e s h E x i t
S e l f R e f r e s h E n t r y
A u t o R e f r e s h
:
D o n ' t c a r e
*Note: TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 40/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
