ESMT
(Preliminary)
M12L128324A (2E)
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
* N o t e 2
tS S
tS S
tS S
* N o t e 1
C K E
* N o t e 3
C S
R A S
C A S
A D D R
R a
C a
B A 1
B A 0
A10/AP
R a
tS H Z
D Q
Qa1 Qa2
Qa0
W E
D Q M
Read
P r e c h a r g e
Pr ech ar ge
Row A c t i ve
Pow er - D ow n
E ntr y
Pr ech arge
Pow er - D ow n
Exi t
A c t i v e
P o w e r - d o w n
E x i t
A ct ive
Pow er - dow n
E ntr y
:
D o n ' t c a r e
*Note: 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 39/44