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Epson Research and Development
Vancouver Design Center
7.1.5 Motorola MC68K Bus 1 Interface Timing (e.g. MC68000)
TCLK
t2 t3
CLK
t4
t5
A[20:1]
M/R#
t6
CS#
AS#
t17
t11
t8
UDS#
LDS#
t7
R/W#
t9
t10
DTACK#
t12
t13
D[15:0](write)
t14
t16
t15
D[15:0](read)
Figure 7-5: Motorola MC68000 Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06