Epson Research and Development
Page 55
Vancouver Design Center
Table 7-4: MIPS/ISA Timing
3.0V
5.0V
Symbol
Parameter
Min
Max
Min
Max
Units
fBUSCLK Clock frequency
TBUSCLK Clock period
50
50
MHz
ns
1/fBUSCLK
1/fBUSCLK
t2
t3
Clock pulse width high
Clock pulse width low
6
6
6
6
ns
ns
LatchA20, SA[19:0], M/R#, SBHE# setup to first
BUSCLK where CS# = 0 and either MEMR# = 0 or
MEMW# = 0
t4
4
3
ns
LatchA20, SA[19:0], M/R#, SBHE# hold from rising edge
of either MEMR# or MEMW#
t5
t6
t7
0
0
2
0
0
2
ns
ns
ns
CS# hold from rising edge of either MEMR# or MEMW#
Falling edge of either MEMR# or MEMW# to IOCHRDY#
driven low
17
12
10
7
Rising edge of either MEMR# or MEMW# to IOCHRDY#
tri-state
t8
t9
2
0
1
0
ns
ns
SD[15:0] setup to third BUSCLK where CS# = 0
MEMW# = 0 (write cycle)
t10
t11
t12
t13
SD[15:0] hold (write cycle)
0
4
0
7
0
3
0
4
ns
ns
ns
ns
Falling edge MEMR# to SD[15:0] driven (read cycle)
SD[15:0] setup to rising edge IOCHRDY# (read cycle)
Rising edge of MEMR# toSD[15:0] tri-state (read cycle)
31
15
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
