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Epson Research and Development
Vancouver Design Center
7.1.6 Motorola MC68K Bus 2 Interface Timing (e.g. MC68030)
TCLK
t2
t3
CLK
t4
t5
A[20:0]
SIZ[1:0] M/R#
t6
CS#
AS#
t17
t11
DS#
t7
t8
R/W#
t9
t10
DSACK1#
D[31:16](write)
D[31:16](read)
t12
t13
t16
t14
t15
Figure 7-6: Motorola MC68030 Timing
Note
The above timing diagram is not applicable if MD12 = 1 (BUSCLK divided by 2).
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06