Epson Research and Development
Page 33
Vancouver Design Center
Table 5-1: Host Bus Interface Pin Descriptions (Continued)
RESET#
State
Pin Name
Type
Pin #
Cell
Description
This is a multi-purpose pin:
• For SH-3/SH-4 Bus, this pin inputs the read signal (RD#).
• For MC68K Bus 1, this pin is connected to VDD
• For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).
.
• For Generic Bus, this pin inputs the read command for the lower
data byte (RD0#).
• For MIPS/ISA Bus, this pin inputs the memory read signal
(MEMR#).
RD#
I
7
CS
Hi-Z
• For Philips PR31500/31700 Bus, this pin inputs the memory read
command (/RD).
• For Toshiba TX3912 Bus, this pin inputs the memory read command
(RD*).
• For PowerPC Bus, this pin inputs the transfer size 0 signal (TSIZ0).
• For PC Card (PCMCIA) Bus, this pin inputs the output enable signal
(OE#).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
This is a multi-purpose pin:
• For SH-3/SH-4 Bus, this pin inputs the write enable signal for the
lower data byte (WE0#).
• For MC68K Bus 1, this pin must be connected to VDD
• For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic Bus, this pin inputs the write enable signal for the lower
data byte (WE0#).
• For MIPS/ISA Bus, this pin inputs the memory write signal
(MEMW#).
WE0#
I
8
CS
Hi-Z
• For Philips PR31500/31700 Bus, this pin inputs the memory write
command (/WE).
• For Toshiba TX3912 Bus, this pin inputs the memory write
command (WE*).
• For PowerPC Bus, this pin inputs the Transfer Size 1 signal (TSIZ1).
• For PC Card (PCMCIA) Bus, this pin inputs the write enable signal
(WE#).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
