Epson Research and Development
Page 31
Vancouver Design Center
Table 5-1: Host Bus Interface Pin Descriptions (Continued)
RESET#
State
Pin Name
Type
Pin #
Cell
Description
These pins are the system data bus. For 8-bit bus modes, unused data
pins should be tied to VDD
.
• For SH-3/SH-4 Bus, these pins are connected to D[15:0].
• For MC68K Bus 1, these pins are connected to D[15:0].
• For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit
devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g.
MC68340).
• For Generic Bus, these pins are connected to D[15:0].
• For MIPS/ISA Bus, these pins are connected to SD[15:0].
DB[15:0]
IO
16-31
C/TS2
Hi-Z
• For Philips PR31500/31700 Bus, pins DB[15:8] are connected to
D[23:16] and pins DB[7:0] are connected to D[31:24].
• For Toshiba TX3912 Bus, pins DB[15:8] are connected to D[23:16]
and pins DB[7:0] are connected to D[31:24].
• For PowerPC Bus, these pins are connected to D[0:15].
• For PC Card (PCMCIA) Bus, these pins are connected to D[15:0].
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
This is a multi-purpose pin:
• For SH-3/SH-4 Bus, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For MC68K Bus 1, this pin inputs the upper data strobe (UDS#).
• For MC68K Bus 2, this pin inputs the data strobe (DS#).
• For Generic Bus, this pin inputs the write enable signal for the upper
data byte (WE1#).
• For MIPS/ISA Bus, this pin inputs the system byte high enable
signal (SBHE#).
CS/TS
2
WE1#
IO
9
Hi-Z
• For Philips PR31500/31700 Bus, this pin inputs the odd byte access
enable signal (/CARDxCSH).
• For Toshiba TX3912 Bus, this pin inputs the odd byte access enable
signal (CARDxCSH*).
• For PowerPC Bus, this pin outputs the burst inhibit signal (BI#).
• For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal
(CE2#).
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
• For Philips PR31500/31700 Bus, this pin is connected to VDD
.
• For Toshiba TX3912 Bus, this pin is connected to VDD
.
• For all other busses, this input pin is used to select between the
display buffer and register address spaces of the S1D13506. M/R#
is set high to access the display buffer and low to access the
registers. See Register Mapping.
M/R#
CS#
I
I
5
4
C
C
Hi-Z
Hi-Z
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40.
• For Philips PR31500/31700 Bus, this pin is connected to VDD
• For Toshiba TX3912 Bus, this pin is connected to VDD
• For all other busses, this is the Chip Select input.
.
.
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40. See the
respective AC Timing diagram for detailed functionality.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
