Epson Research and Development
Page 29
Vancouver Design Center
5.2 Pin Description
Key:
I
=
=
=
=
=
=
=
=
=
Input
O
Output
IO
A
Bi-Directional (Input/Output)
Analog
P
Power pin
C
CMOS level input
CD
CS
COx
CMOS level input with pull down resistor (typical values of 50Ω/90ΚΩ at 5V/3.3V respectively)
CMOS level Schmitt input
CMOS output driver, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
Tri-state CMOS output driver, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V), x denotes
driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
TSx
=
=
=
TSu
TSx with pull up resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V respectively)
TSx with pull down resistor, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V) (typical
values of 100KΩ/180ΚΩ at 5V/3.3V)
TSxD
CNx
=
=
=
CMOS low-noise output driver, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
CNx with pull up resistor, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
CNx with pull down resistor, x denotes driver type (1=4/-4mA, 2=8/-8mA, 3=12/-12mA @ 5V)
CNxU
CNxD
5.2.1 Host Bus Interface
Table 5-1: Host Bus Interface Pin Descriptions
RESET#
State
Pin Name
Type
Pin #
Cell
Description
• For SH-3/SH-4 Bus, this pin must be connected to VSS or VDD
.
• For MC68K Bus 1, this pin inputs the lower data strobe (LDS#).
• For MC68K Bus 2, this pin inputs system address bit 0 (A0).
• For Generic Bus, this pin must be connected to VSS or VDD
.
• For MIPS/ISA Bus, this pin inputs system address bit 0 (SA0).
• For Philips PR31500/31700 Bus, this pin inputs system address bit
0 (A0).
AB0
I
3
CS
Hi-Z
• For Toshiba TX3912 Bus, this pin inputs system address bit 0 (A0).
• For PowerPC Bus, this pin inputs system address bit 31 (A31).
• For PC Card (PCMCIA) Bus, this pin must be connected to VSS or
VDD
.
SeeTable 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
• For PowerPC Bus, these pins input the system address bits 19
through 30 (A[19:30]).
• For all other busses, these pins input the system address bits 12
through 1 (A[12:1]).
119-128,
1, 2
AB[12:1]
I
C
Hi-Z
See Table 5-7:, “CPU Interface Pin Mapping,” on page 40 for summary.
See the respective AC Timing diagram for detailed functionality.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
