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Epson Research and Development
Vancouver Design Center
11.1.3 Examples
Example 20: Enable the CRT display. Assume the CRT timing registers are already
programmed.
1. Confirm the TV PAL/NTSC Output Select bit is clear. REG[05Bh] bit 0 is set to 0.
2. Confirm the CRT and TV displays are disabled. REG[1FCh] bits 2-1 are set to 0.
3. Enable the CRT. REG[1FCh] is set to 1.
Sample code demonstrating how to enable the CRT display is provided in the file
56_CRT.c. This file is available on the internet at www.eea.epson.com.
11.2 TV Considerations
TV timings are based on either the NTSC or PAL specifications. The TV display can be
output in either composite video or S-video format.
11.2.1 NTSC Timings
NTSC timings require a 14.318 MHz input clock. With the correct input clock the
following resolutions are supported.
• 640x480
• 696x436
• 752x484
11.2.2 PAL Timings
PAL timings require a 17.734 MHz input clock. With the correct input clock the following
resolutions are supported.
• 640x480
• 800x572
• 856x518
• 920x572
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
