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S1D13506 参数 Datasheet PDF下载

S1D13506图片预览
型号: S1D13506
PDF下载: 下载PDF文件 查看货源
内容描述: S1D13506彩色LCD / CRT / TV控制器 [S1D13506 Color LCD/CRT/TV Controller]
分类和应用: 电视控制器
文件页数/大小: 696 页 / 5934 K
品牌: EPSON [ EPSON COMPANY ]
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Page 92  
Epson Research and Development  
Vancouver Design Center  
BltMemoryOffset = ScreenStride ÷ 2  
= 640 ÷ 2  
= 320  
= 140h  
REG[10Dh] is set to 01h and REG[10Ch] is set to 40h.  
8. Calculate the number of WORDS the blit engine expects to receive.  
nWORDS = ((BlitWidth + 1 + DestinationPhase) ÷ 2) × BlitHeight  
= (100 + 1 + 0) ÷ 2 × 20  
= 1000  
= 3E8h  
9. Program the BitBLT Destination/Source Linear Select bits for a rectangular blit (Bit-  
BLT Destination Linear Select = 0, BitBLT Source Linear Select = 0).  
Start the blit operation and wait for the blit engine to start. REG[100h] is set to 80h,  
then wait until REG[100h] bit 7 returns a 1.  
10. Prior to reading all nWORDS from the Blit FIFO, confirm the Blit FIFO is not empty  
(REG[100h] bit 4 returns a 1). If the BitBLT FIFO Not Empty Status returns a 1 and  
the BitBLT FIFO Half Full Status returns a 0 then you can read up to 8 WORDS. If  
the BitBLT FIFO Full Status returns a 1, read up to 16 WORDS. If the BitBLT FIFO  
Not Empty Status returns a 0 (the FIFO is empty), do not read from the BitBLT FIFO  
until it returns a 1.  
The following table summarizes how many words can be read from the Blit FIFO.  
Table 10-7: Possible Blit FIFO Reads  
BitBLT Control Register 0 (REG[100h])  
Word Reads  
Available  
FIFO Not Empty Status  
FIFO Half Full Status  
FIFO Full Status  
0
1
1
1
0
0
1
1
0
0
0
1
0 (do not read)  
up to 8  
8
16  
Note  
The order of register initialization is irrelevant as long as all relevant registers are pro-  
grammed before the BitBLT is initiated.  
10.3 S1D13506 BitBLT Synchronization  
A BitBLT operation can only be started if the blit engine is not busy servicing another blit.  
Before a new BitBLT operation is started, software must confirm the BitBLT Active Status  
bit (REG[100h] bit 7) returns a 0. Software can either test this bit after each BitBLT  
operation, or before each BitBLT operation.  
Testing the BitBLT Status After  
S1D13506  
X25B-G-003-03  
Programming Notes and Examples  
Issue Date: 01/02/06  
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