Page 100
Epson Research and Development
Vancouver Design Center
12.2 Considerations
Software can determine if the MediaPlug interface is enabled or disabled by reading the
MD Configuration Readback Register (REG[00Dh]) and masking the data with 60h. If the
masked result equals 60h, the MediaPlug Interface is enabled.
When the MediaPlug interface is enabled, FPDAT[15:8] are used exclusively for the
MediaPlug interface. Therefore, when the MediaPlug interface is enabled, Color 16-bit
panels cannot be used without an external multiplexing circuit. For further information on
the external circuit required, see the S1D13506 Hardware Functional Specification,
document number X25B-A-001-xx.
The MediaPlug interface requires a source clock between 8MHz and 19MHz to operate
(optimal is 14.318MHz). By default, the MediaPlug software assumes a 14.318MHz
frequency is available on CLKI2. If the frequency of CLKI2 is changed, software should
reprogram the MediaPlug Clock Register (REG[01Ch]) to select a clock source that is
suitable, or program the clock divide bits to obtain a frequency within the correct range.
If the S5U13506B00x evaluation board is used, the clock chip should be programmed to
support a valid clock for the MediaPlug interface. The ICD2061A clock chip selects
frequencies based on the states of GPIO1 and GPIO2. Since the MediaPlug interface uses
the GPIO2 pin for camera power, it is important to program the clock chip for the correct
MediaPlug interface frequency when the camera is both on or off (GPIO2 low or high). A
HAL function is available which programs the clock chip for the MediaPlug interface.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
