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S1D13506 参数 Datasheet PDF下载

S1D13506图片预览
型号: S1D13506
PDF下载: 下载PDF文件 查看货源
内容描述: S1D13506彩色LCD / CRT / TV控制器 [S1D13506 Color LCD/CRT/TV Controller]
分类和应用: 电视控制器
文件页数/大小: 696 页 / 5934 K
品牌: EPSON [ EPSON COMPANY ]
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Epson Research and Development  
Page 97  
Vancouver Design Center  
11.2.3 TV Filters  
The S1D13506 is designed with three filters which improve TV picture quality.  
• Flicker Filter.  
• Chrominance Filter.  
• Luminance Filter.  
Each filter is independent and can be enabled/disabled separately. The TV picture quality  
varies depending on the actual picture displayed (static image, moving image, number of  
colors etc.) and may be improved using the filters.  
Flicker Filter  
The Flicker Filter is controlled by the Display Mode Select bits (REG[1FCh] bits 2-0). It  
reduces the “flickering” effect seen on interlaced displays caused by sharp vertical image  
transitions that occur over one line (e.g. one pixel high lines, edges of window boxes, etc.).  
The Flicker Filter may be used to for both composite video and S-video formats.  
Note  
The CRT/TV PCLK 2X Enable bit (REG[018h] bit 7) must be set to 1 when the Flicker  
Filter is enabled.  
Chrominance Filter  
The Chrominance Filter is controlled by the TV Chrominance Filter Enable bit  
(REG[05Bh] bit 5). It adjusts the color of the TV, reducing the “ragged edges” seen a the  
boundaries between sharp color transitions. The Chrominance Filter may improve the TV  
picture quality when in composite video format.  
Luminance Filter  
The Luminance Filter is controlled by the TV Luminance Filter Enable bit (REG[05Bh] bit  
4). It adjusts the brightness of the TV, reducing the “rainbow-like” colors at the boundaries  
between sharp brightness transitions. The Luminance Filter may improve the TV picture  
quality when in composite video format.  
For further information on the TV filters, see the S1D13506 Hardware Functional Specifi-  
cation, document number X25B-A-001-xx.  
11.2.4 Examples  
Example 21: Enable the TV display and set the Flicker Filter. Assume the TV timing  
registers are already programmed.  
1. Enable the TV with Flicker Filter enabled. REG[1FCh] is set to 06h.  
2. Enable the CRT/TV PCLK 2X bit (REG[018h] bit 7). REG[018h] bit 7 is set to 1b.  
Programming Notes and Examples  
Issue Date: 01/02/06  
S1D13506  
X25B-G-003-03  
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