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Epson Research and Development
Vancouver Design Center
Testing the BitBLT Status Before
Testing the BitBLT Active Status before starting a new BitBLT results in better perfor-
mance, as both CPU and blit engine can be running at the same time. This is most useful
for BitBLTs that are self completing (once started they don’t require any CPU assistance).
While the blit engine is busy, the CPU can do other tasks. To test before each BitBLT
operation, perform the following.
1. Wait for the current BitBLT operation to finish -- Poll the BitBLT Active Status bit
(REG[100h] bit 7) until it returns a 0.
2. Program and start the new BitBLT operation.
3. Continue the program (CPU and blit engine work independently).
However, this approach can pose problems if the CPU writes a pixel while the blit engine
is running a blit. If the CPU writes the pixel before the BitBLT finishes, the pixel may be
overwritten by the blit. To avoid this scenario, always assure no BitBLT is in progress
before accessing the display buffer with the CPU, or don’t use the CPU to access display
buffer at all.
10.4 S1D13506 BitBLT Known Limitations
The S1D13506 blit engine has the following limitations.
• BitBLT Width must be greater than 0.
• BitBLT Height must be greater than 0.
• The blit engine is not SwivelView aware. If BitBLTs are used when SwivelView is
enabled, the coordinates and verticies are swapped. It may be possible to recalculate
these coordinates and vertices allowing use of some of the BitBLT functions. However
the coordinate transformations required may nullify the benefits of the BitBLT.
• The Pattern Fill with ROP (0Ch or 03h) and Transparent Pattern Fill are designed such
that the BitBLT Width must be > 1 for 15/16 bpp color depths and > 2 for 8 bpp.
10.5 Sample Code
Sample code demonstrating how to program the S1D13506 BitBLT engine is provided in
the file 13506BLT.ZIP. This file is available on the internet at www.eea.epson.com.
S1D13506
X25B-G-003-03
Programming Notes and Examples
Issue Date: 01/02/06