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Epson Research and Development
Vancouver Design Center
8.3.9 CRT/TV Display Mode Registers
CRT/TV Display Mode Register
REG[060h]
RW
CRT/TV Bit-
per-pixel
Select Bit 2
CRT/TV Bit-
per-pixel
Select Bit 1
CRT/TV Bit-
per-pixel
Select Bit 0
CRT/TV
Display Blank
n/a
n/a
n/a
n/a
bit 7
CRT/TV Display Blank
When this bit = 1 the CRT/TV display pipeline is disabled and all CRT/TV data outputs
are forced to zero (i.e., the screen is blanked).
When this bit = 0 the CRT/TV display pipeline is enabled.
bits 2-0
CRT/TV Bit-per-pixel Select Bits [2:0]
These bits select the bit-per-pixel for the displayed data.
Note
15/16 bpp color depths bypass the LUT.
Table 8-23: CRT/TV Bit-per-pixel Selection
Bit-per-pixel Select Bits [2:0]
Color Depth (bpp)
Reserved
Reserved
4 bpp
000
001
010
011
8 bpp
100
15 bpp
101
16 bpp
110-111
Reserved
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
