Page 146
Epson Research and Development
Vancouver Design Center
CRT/TV HRTC Start Position Register
REG[053h]
RW
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
n/a
n/a
HRTC Start
HRTC Start
HRTC Start
HRTC Start
HRTC Start
HRTC Start
Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0
bits 5-0
CRT/TV HRTC Start Position Bits [5:0]
For CRT/TV, these bits specify the delay, in 8 pixel resolution, from the start of the hori-
zontal non-display period to the leading edge of the HRTC pulse.
The following equations can be used to determine the HRTC start position in number of
pixels for each display type:
HRTC start position in number of pixels=:
[(ContentsOfThisRegister) x 8 + 3] for CRT with 4/8 bpp color depth
[(ContentsOfThisRegister) x 8 + 5] for CRT in 15/16 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 7] for TV-NTSC in 4/8 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 5] for TV-NTSC in 15/16 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 7] for TV-PAL in 4/8 bpp color depth
[((ContentsOfThisRegister) + 1) x 8 - 5] for TV-PAL in 15/16 bpp color depth
Note
REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1)
CRT HRTC Pulse Width Register
REG[054h]
RW
CRT HRTC
Polarity
Select
CRT HRTC
Pulse Width
Bit 3
CRT HRTC
Pulse Width
Bit 2
CRT HRTC
Pulse Width
Bit 1
CRT HRTC
Pulse Width
Bit 0
n/a
n/a
n/a
bit 7
CRT HRTC Polarity Select
This bit selects the polarity of HRTC for CRTs.
When this bit = 1, the HRTC pulse is active high.
When this bit = 0, the HRTC pulse is active low.
Note
For NTSC/PAL modes, this bit must be set to 0b.
bits 3-0
CRT HRTC Pulse Width Bits [3:0]
These bits specify the pulse width of the CRT HRTC output signal in 8 pixel resolution.
HRTC pulse width in number of pixels = ((ContentsOfThisRegister) + 1) × 8
Note
For NTSC/PAL modes, these bits must be set to 0000b.
Note
REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
