Page 148
Epson Research and Development
Vancouver Design Center
CRT/TV VRTC Start Position Register
REG[059h]
RW
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
CRT/TV
n/a
VRTC Start
VRTC Start
VRTC Start
VRTC Start
VRTC Start
VRTC Start
VRTC Start
Position Bit 6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0
bits 6-0
CRT/TV VRTC Start Position Bits [6:0]
For CRT/TV, these bits specify the delay in lines from the start of the vertical non-display
period to the leading edge of the VRTC pulse.
VRTC start position in number of lines = (ContentsOfThisRegister) + 1
Note
(REG[058h] bits 5-0 + 1) ≥ (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1)
CRT/TV VRTC Pulse Width Register
REG[05Ah]
RW
CRT VRTC
Polarity
Select
CRT VRTC
Pulse Width
Bit 2
CRT VRTC
Pulse Width
Bit 1
CRT VRTC
Pulse Width
Bit 0
n/a
n/a
n/a
n/a
bit 7
CRT VRTC Polarity Select
This bit selects the polarity of VRTC for CRT.
When this bit = 1, the VRTC pulse is active high.
When this bit = 0, the VRTC pulse is active low.
Note
For PAL/NTSC, this bit must be set to 0b.
bits 2-0
CRT VRTC Pulse Width Bits [2:0]
These bits specify the pulse width of the CRT VRTC output signal in number of lines.
VRTC pulse width in number of lines = (ContentsOfThisRegister) + 1
Note
For NTSC/PAL modes, these bits should be set to 000b.
Note
(REG[058h] bits 5-0 + 1) ≥ (REG[059h] + 1) + (REG[05Ah] bits 2-0 + 1)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
