Epson Research and Development
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Vancouver Design Center
LCD Display FIFO Low Threshold Control Register
REG[04Bh]
RW
LCD Display LCD Display LCD Display LCD Display LCD Display LCD Display
FIFO Low
Threshold
Bit 5
FIFO Low
Threshold
Bit 4
FIFO Low
Threshold
Bit 3
FIFO Low
Threshold
Bit 2
FIFO Low
Threshold
Bit 1
FIFO Low
Threshold
Bit 0
n/a
n/a
bits 5-0
LCD Display FIFO Low Threshold Bits [5:0]
When this register is set to 00h, the threshold is automatically set in hardware. If it
becomes necessary to adjust REG[04Ah] from its default value, then the following
formula must be maintained:
REG[04Bh] > REG[04Ah] and REG[04Bh] ≤ 3Ch
8.3.8 CRT/TV Configuration Registers
CRT/TV Horizontal Display Width Register
REG[050h]
RW
CRT/TV
Horizontal
CRT/TV
Horizontal
CRT/TV
Horizontal
CRT/TV
Horizontal
CRT/TV
Horizontal
CRT/TV
Horizontal
CRT/TV
Horizontal
n/a
Display Width Display Width Display Width Display Width Display Width Display Width Display Width
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
bits 6-0
CRT/TV Horizontal Display Width Bits [6:0]
These bits specify the CRT/TV horizontal display width, in 8 pixel resolution.
Horizontal display width in number of pixels = ((ContentsOfThisRegister)+ 1) × 8
CRT/TV Horizontal Non-Display Period Register
REG[052h]
RW
CRT/TV
Horizontal
Non-Display
Period Bit 0
CRT/TV
Horizontal
Non-Display
Period Bit 5
CRT/TV
CRT/TV
Horizontal
Non-Display
Period Bit 3
CRT/TV
Horizontal
Non-Display
Period Bit 2
CRT/TV
Horizontal
Non-Display
Period Bit 1
Horizontal
Non-Display
Period Bit 4
n/a
n/a
bits 5-0
CRT/TV Horizontal Non-Display Period Bits [5:0]
These bits specify the CRT/TV horizontal non-display period width in 8 pixel resolution.
Horizontal non-display period width in number of pixels =
((ContentsOfThisRegister) + 1) × 8 for CRT mode
(ContentsOfThisRegister) × 8 + 6 for TV mode with NTSC output
(ContentsOfThisRegister) × 8 + 7 for TV mode with PAL output
Note
For CRT mode, the recommended minimum value which should be programmed into
this register is 3 (32 pixels).
Note
REG[052h] + 1 ≥ (REG[053h] + 1) + (REG[054h] bits 3-0 + 1)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
