EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
6.2.11 IOCF0 (Interrupt Mask Register)
7
6
5
4
3
2
1
0
CMPIE
PWM3IE PWM2IE PWM1IE
ADIE
EXIE
ICIE
TCIE
NOTE
■ IOCF0 register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the IOCF0 to "1."
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (CMPIE): CMPIF interrupt enable bit
0 = Disable CMPIF interrupt
1 = Enable CMPIF interrupt
When the Comparator output status change is used to enter
interrupt vector or to enter next instruction, the CMPIE bit must be
set to “Enable.“
Bit 6 (PWM3IE): PWM3IF interrupt enable bit
0 = Disable PWM3 interrupt
1 = Enable PWM3 interrupt
Bit 5 (PWM2IE): PWM2IF interrupt enable bit
0 = Disable PWM2 interrupt
1 = Enable PWM2 interrupt
Bit 4 (PWM1IE): PWM1IF interrupt enable bit
0 = Disable PWM1 interrupt
1 = Enable PWM1 interrupt
Bit 3 (ADIE):
ADIF interrupt enable bit
0 = Disable ADIF interrupt
1 = Enable ADIF interrupt
When the ADC Complete is used to enter interrupt vector or to enter
next instruction, the ADIE bit must be set to “Enable.“
Bit 2 (EXIE):
Bit 1 (ICIE):
EXIF interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
If Port6 Input Status Change Interrupt is used to enter interrupt
vector or to enter next instruction, the ICIE bit must be set to
“Enable.“
24 •
Product Specification (V1.0) 06.23.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
