EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
6.2.19 IOCC1 (TMR1L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM1 Timer)
The content of IOCC1 is read-only.
6.2.20 IOCD1 (TMR2L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM2 Timer)
The content of IOCD1 is read-only.
6.2.21 IOCE1 (TMR3L: the Least Significant Byte (Bit 7 ~ Bit 0) of
PWM3 Timer)
The content of IOCE1 is read-only.
6.2.22 IOCF1 (TMRH: the Most Significant Bits of PWM Timer)
7
6
5
4
3
2
1
0
“0”
“0”
TMR3[9] TMR3[8] TMR2[9] TMR2[8] TMR1[9] TMR1[8]
The content of IOCF1 is read-only.
Bit 7 & Bit 6:
Unimplemented, read as ‘0’.
Bit 5 & Bit 4 (TMR3[9], TMR3[8]): The Most Significant Bits of PWM1Timer
Bit 3 & Bit 2 (TMR2[9], TMR2[8]):The Most Significant Bits of PWM2Timer
Bit 1 & Bit 0 (TMR1[9], TMR1[8]):The Most Significant Bits of PWM3Timer
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT respectively.
The PST0 ~ PST2 bits of the CONT register are used to determine the ratio of the TCC
prescaler, and the PWR0 ~ PWR2 bits of the IOCE0 register are used to determine the
prescaler of WDT. The prescaler counter is cleared by the instructions each time such
instructions are written into TCC. The WDT and prescaler will be cleared by the
“WDTC” and “SLEP” instructions. Fig. 6-2 (next page) depicts the block diagram of
TCC/WDT.
TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock or
external signal input (edge selectable from the TCC pin). If TCC signal source is from
internal clock, TCC will increase by 1 at every instruction cycle (without prescaler).
Referring to Fig. 6-2, CLK=Fosc/2 or CLK=Fosc/4 is dependent to the CODE Option bit
<CLKS>. CLK=Fosc/2 if the CLKS bit is "0," and CLK=Fosc/4 if the CLKS bit is "1." If
TCC signal source is from external clock input, TCC will increase by 1 at every falling
edge or rising edge of the TCC pin. TCC pin input time length (kept in High or Low
level) must be greater than 1CLK.
NOTE
The internal TCC will stop running when sleep mode occurs. However, during AD
conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of RE register is
enabled, the TCC will keep on running
26 •
Product Specification (V1.0) 06.23.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
