EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
Bit 2: Bit 0 ( T2P2:T2P0 ): TMR2 clock prescale option bits
T2P2
T2P1
T2P0
Prescale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2(default)
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.6 IOCA0 (CMPCON: Comparator Control Register)
7
6
5
4
3
2
1
0
“0”
“0”
“0”
“0”
“0”
CPOUT
COS1
COS0
Bit 7 ~ Bit 3: Unimplemented, read as ‘0’
Bit 2 (CPOUT): the result of the comparator output
Bit 1 ~ Bit 0 (COS1 ~ COS0): Comparator/OP Select bits
COS1 COS0
Function Description
0
0
0
1
Comparator and OP not used. P60 acts as normal I/O pin
Acts as Comparator and P60 acts as normal I/O pin
Acts as Comparator and P60 acts as Comparator output
pin (CO)
1
1
0
1
Acts as OP and P60 acts as OP output pin (CO)
NOTE
■ The CO and ADEO of the P60/ADE0/CO pins cannot be used at the same time.
■ The P60/ADE0/CO pin priority is as follows:
P60/ADE0/CO PRIORITY
High
CO
Medium
ADE0
Low
P60
6.2.7 IOCB0 (Pull-Down Control Register)
7
6
5
4
3
2
1
0
/PD7
/PD6
/PD5
/PD4
/PD3
/PD2
/PD1
/PD0
IOCB0 register is both readable and writable
Bit 7 (/PD7): Control bit is used to enable the pull-down of the P67 pin
0 = Enable internal pull-down
1 = Disable internal pull-down
Product Specification (V1.0) 06.23.2005
• 21
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
